Ask a room of engineering students who wants to design chips and most hands go up. Ask who wants to verify them and the room gets honest.
The part of the job nobody applies for
The public picture of chip design is architecture: someone deciding what the processor does, how many cores it has, how the memory hierarchy works. That work exists, it is genuinely interesting, and it is a small fraction of the headcount.
On a typical digital chip project the largest single block of engineering effort is verification, and on complex designs verification engineers routinely outnumber design engineers. It is also, consistently, the hardest group to hire into.
The reason the imbalance persists is a misunderstanding of what verification is. It is widely imagined as testing: running the design and checking the output. It is closer to the opposite. A verification engineer builds an independent model of what the design is supposed to do, constructs an environment that generates stimulus the designer did not anticipate, measures which behaviours have actually been exercised, and argues from coverage that the remaining risk is acceptable.
Verification is not checking that the design works. It is building the argument that it cannot fail in a way you have not looked for.
That is a design activity with its own methodology, its own languages and its own intellectual difficulty. Teams that treat it as junior work staff it accordingly and then discover the consequence at tape-out.
What the direction covers
The scope: digital design, hardware description languages, verification, physical design, timing and power analysis, and design for test.
Four areas.
Register transfer level design. Describing hardware behaviour in a hardware description language, in a style that synthesises into gates.
Verification. Constrained random stimulus, functional coverage, assertion based methods and formal techniques.
Physical design. Floorplanning, placement, clock distribution, routing and timing closure.
Analysis and test. Static timing, power, signal integrity and the structures that make a manufactured chip testable.
Why a chip is not software
The single most consequential difference, and the one that reshapes every process decision in the industry.
There is no patch. A functional bug discovered after manufacture is fixed by changing the design and producing a new mask set, which is expensive at mature process nodes and extremely expensive at leading ones, and which costs months. A bug found after the product ships may be fixable only by working around it in software, or not at all.
The design is parallel by nature. Hardware description languages describe structures that all exist simultaneously. Software engineers moving into hardware typically write sequential code that simulates correctly and either fails to synthesise or synthesises into something enormous. The conceptual shift is from instructions executing in order to logic existing at once.
Timing is physical. A design is not correct in the abstract. It is correct at a clock frequency, at a voltage, at a temperature, across manufacturing variation, and each of those corners must be shown to close.
Everything costs area, and area costs money. Die area maps directly to yield and to cost per chip. A feature that would be free in software has a permanent unit cost in silicon.
These four facts explain why the industry's process looks conservative from outside. It is not conservatism. It is the appropriate response to a one shot manufacturing step.
Physical design, where the schedule actually goes
Between a verified register transfer description and a manufacturable layout there is a body of work that outsiders often assume is automated.
Tools do enormous amounts of it. They do not remove the engineering.
Timing closure. The design must meet its timing constraints on every path at every corner. Paths that fail are fixed by resizing, restructuring logic, moving blocks, adjusting the floorplan, or changing the architecture. The last option is common enough that treating physical design as a downstream step produces schedules that do not hold.
Power and thermal. Both static and switching power must be managed, along with the voltage drop across the power delivery network and the hot spots that dense activity creates.
Routability. A floorplan that is comfortable for placement may be impossible to route, and finding that out late costs weeks.
Clock distribution. Delivering the clock across a large die with controlled skew is a specialism, and it consumes a meaningful share of total chip power.
Physical design engineers are scarce, the skill takes years to build, and it is largely invisible in how the industry is described to students.
Where this sits in the domain
Chip design and VLSI is the third of nine directions in Astra Trainer's semiconductors, electronics and quantum domain. It connects directly to semiconductor physics and devices, since every timing and power model rests on device behaviour, and to semiconductor manufacturing and advanced packaging, where the design meets the process that will build it.
It also connects outward to AI and computing, where accelerator design is now a large share of new chip starts. Partners usually scope chip design alongside embedded systems, because the hardware and software teams on a system-on-chip programme need a shared vocabulary. You can see the nine directions here.
Design for test, which is not optional
A manufactured chip must be tested, and the structures that make that possible are added to the design deliberately.
Scan chains connect the design's storage elements into shift registers so internal state can be loaded and observed. Built-in self test structures allow memories and analogue blocks to test themselves. Boundary scan allows connections between packaged chips on a board to be checked. Test compression reduces how much data has to be pushed through a tester, because tester time is expensive and scales with volume.
All of this occupies die area and consumes design effort on functionality the customer will never use. It is included anyway, for a reason worth stating directly.
Manufacturing yield is never one hundred percent. Defects occur. A chip that cannot be tested cannot be screened, which means defective parts reach customers, which in automotive, medical and industrial applications is a safety and liability problem rather than a quality statistic.
The recurring mistake is deciding test structures late, when the floorplan is settled and adding them is disruptive. Test insertion is a design decision, made early, alongside the architecture.
The roles, named
Register transfer level design engineers. The role most people picture.
Design verification engineers. The largest group on most projects and the hardest to fill.
Physical design engineers. Floorplanning through timing closure.
Static timing analysis and signoff engineers.
Design for test engineers. Scan, self test and compression.
Analogue and mixed signal design engineers. Persistently scarce, because the skill resists automation.
Formal verification engineers, proving properties rather than simulating them.
Computer architects. The smallest group, and the one everyone imagines is the whole field.
Electronic design automation engineers, building and maintaining the tool flows the rest of the industry depends on.
Who can be trained into it
Software engineers. The largest available pool, and the conversion works when the parallel model is taught explicitly rather than assumed. Verification in particular rewards software skill, since modern verification environments are large object oriented programs. This is the fastest route into the industry's biggest shortage.
Field programmable gate array engineers. Close adjacency. Hardware description language fluency and timing intuition already exist. What is new is the discipline that comes from not being able to reprogram the part.
Electronics engineers. Into mixed signal design and into physical design, bringing device and layout intuition.
Test engineers from manufacturing. Into design for test, since they know what is untestable and why.
Embedded software engineers. Into verification and system-on-chip integration, already holding the hardware and software boundary.
Physics and mathematics graduates. Into formal verification, where the reasoning is closer to proof than to programming.
Tools, methodology and confidential flows. Chip design depends on commercial electronic design automation tools, process design kits and foundry rules that are supplied under licence and non-disclosure, and that differ between organisations and process nodes. Training builds methodology and concepts. It does not supply tool licences, process design kits, foundry rules or any confidential design flow, and it is not a substitute for the internal qualification that using them requires.
What to take from this
Verification is the largest part of the effort, the largest part of the schedule risk and the largest unfilled group, and it is design work rather than testing.
A chip cannot be patched, which explains the entire shape of the industry's process.
Physical design routinely pushes work back upstream into architecture, so treating it as a downstream step produces schedules that fail.
Design for test costs area and effort on functionality nobody buys, and without it defective parts reach customers.
And software engineers are the largest realistic source of new verification capability, provided somebody teaches the parallel model rather than assuming it transfers.
Why does verification take up so much of a chip project?
Because the manufacturing step is one shot. Verification builds an independent model of intended behaviour, generates stimulus the designer did not anticipate and measures coverage, in order to argue that undiscovered failure modes are unlikely.
Can software engineers move into chip design?
Yes, and verification is the most natural entry point, because modern verification environments are large object oriented programs. The teachable gap is the shift from sequential execution to structures that all exist at once.
Why is physical design not just automation?
Tools do most of the mechanical work, but timing closure, power delivery, routability and clock distribution regularly require restructuring logic or changing the architecture, which means physical design feeds back into design rather than following it.
Why include test structures that customers never use?
Because manufacturing yield is never perfect and an untestable chip cannot be screened for defects. In automotive, medical and industrial applications, shipping unscreened parts is a safety and liability issue.
Which adjacent roles convert well into VLSI work?
Software engineers into verification, field programmable gate array engineers into design, electronics engineers into mixed signal and physical design, manufacturing test engineers into design for test.