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Chip Design & VLSI
Concevez des puces qui marchent dès leur retour de fab.
Le cours complet
- modules
- 89
- thèmes
- 1 057
- min par leçon
- 15
33%
de croissance des effectifs américains des semi-conducteurs d'ici 2030 — à environ 460 000 postes.
Ce que vous saurez faire.
Écrivez du RTL synthétisable pour de vrais datapaths
Étape 2 · RTL & SoC Architecture
Franchissez les domaines d'horloge sans perdre de données
Étape 2 · RTL & SoC Architecture
Construisez bancs de test UVM et preuves formelles
Étape 3 · Functional & Formal Verification
Bouclez le timing du floorplan au signoff
Étape 4 · Synthesis, Timing & Physical Design
Concevez CAN, PLL et amplificateurs
Étape 5 · Analog & Mixed-Signal
Finalisez le tape-out, déboguez le premier silicium
Étape 6 · Test, Tape-Out & Silicon
Sept étapes.Une ascension continue.
D'une simple porte logique à une puce complète, du tape-out à la mise en service.
89modules
en 7 étapes
1 057thèmes
≈ 12 par module
≈264heures
en leçons de 15 minutes
≈3ans
≈17mois
≈9mois
pour finir tout le cours
- 1
Circuit Foundations
Portes, cellules et le kit de procédé
12 modules · 138 thèmes · ≈ 35 h
- 2
RTL & SoC Architecture
RTL, bus, horloges et alimentation
20 modules · 241 thèmes · ≈ 60 h
- 3
Functional & Formal Verification
La preuve que ça marche avant d'être fabriqué
8 modules · 95 thèmes · ≈ 24 h
- 4
Synthesis, Timing & Physical Design
Du netlist à un layout prêt pour signoff
13 modules · 157 thèmes · ≈ 39 h
- 5
Analog & Mixed-Signal
Où les puces rencontrent le monde réel
16 modules · 192 thèmes · ≈ 48 h
- 6
Test, Tape-Out & Silicon
DFT, tape-out et premier silicium
15 modules · 181 thèmes · ≈ 45 h
- 7
Practicum & Capstone
Votre propre bloc, du cahier des charges au signoff
5 modules · 53 thèmes · ≈ 13 h
Mois
061218240369120246
MoisArrivée · ≈ 3 ans · ≈ 17 mois · ≈ 9 mois
Heures et mois sont des estimations : une leçon de 15 minutes par thème, chaque jour.
Chaque module.Chaque thème.
Les titres des modules et des thèmes restent en anglais, la langue du secteur.
Étape 1
Circuit Foundations
Portes, cellules et le kit de procédé
12 modules · 138 thèmes
1Scope of Chip Design and the IC Development Lifecycle10 thèmes
- Digital, Analog, and Mixed-Signal Integrated Circuits
- ASICs, Application-Specific Standard Products, and Systems on Chip
- Standard-Cell, Full-Custom, and Semi-Custom Design
- Relationships Between Architecture, Circuits, and Layout
- Front-End and Back-End Design Responsibilities
- Foundry, IP Provider, Design Team, and Test Engineering Interfaces
- Specification-to-Silicon Development Stages
- Design Reviews, Milestones, and Acceptance Gates
- First-Silicon Success and Design Risk
- Design Deliverables Across the Chip Lifecycle
2Chip Specifications and Engineering Requirements12 thèmes
- Translating Product Needs into Chip Requirements
- Functional Specifications and Operating Modes
- Throughput, Latency, and Real-Time Constraints
- Power Budgets and Energy per Operation
- Die Area and Package Interface Constraints
- Supply Voltage and Temperature Operating Ranges
- Clock, Reset, and Startup Requirements
- Electrical Interface Specifications
- Testability, Debug, and Observability Requirements
- Reliability and Mission-Profile Requirements
- Requirement Traceability and Acceptance Criteria
- Resolving Conflicting Specifications
3Technology Platforms and Process Design Kits12 thèmes
- Selecting a Process for an IC Application
- Mature-Node and Advanced-Node Design Tradeoffs
- Core, I/O, and Specialty Device Options
- Process Design Kit Organization
- Schematic Symbols and Parameterized Cells
- Device Models and Supported Operating Conditions
- Process Corners and Statistical Model Files
- Layer Maps and Technology Files
- Design Rules and Verification Decks
- Standard-Cell, Memory, and I/O Library Availability
- PDK Version Control and Tool Compatibility
- Process Migration and Portability Constraints
4Design Representations and EDA Workflows11 thèmes
- Behavioral, RTL, Gate-Level, and Transistor-Level Models
- Hierarchical Schematics and Netlists
- Logical and Physical Design Hierarchies
- Liberty Timing and Power Libraries
- LEF Abstracts and DEF Implementation Data
- SDC Timing Constraints and UPF Power Intent
- SPEF Parasitics and SDF Timing Annotation
- GDSII and OASIS Layout Deliverables
- Model Consistency Across Design Views
- EDA Tool Inputs, Outputs, and Dependencies
- Reproducible Run Directories and Design Checkpoints
5CMOS Devices for Circuit Designers12 thèmes
- MOS Operating Regions in Circuit Design
- Bias Points and Available Voltage Headroom
- Transconductance and Output Resistance
- Intrinsic Gain and Transit-Frequency Tradeoffs
- Gate, Junction, and Overlap Capacitances
- Body Effect and Body-Bias Options
- Threshold-Voltage Choices and Leakage Tradeoffs
- Short-Channel Effects in Circuit Models
- Device Sizing and Finger Configuration
- Safe Device Voltages and Model Validity
- PVT Sensitivity of Circuit Behavior
- Device Matching and Statistical Variation
6Integrated Passives and Interconnect Models10 thèmes
- On-Chip Resistor Types and Design Tradeoffs
- Integrated Capacitor Types and Parasitics
- Voltage and Temperature Dependence of Passives
- Metal Resistance and Via Resistance
- Ground and Coupling Capacitance
- Distributed RC Interconnect Models
- Inductance in Clock, Power, and I/O Structures
- Interconnect Scaling and Wire-Dominated Delay
- Passive Matching and Layout Dependence
- Extracted Networks and Model Reduction
7Circuit Simulation and Characterization13 thèmes
- SPICE Netlists and Hierarchical Testbenches
- Operating-Point Analysis and Bias Debugging
- DC Sweeps and Transfer Characteristics
- Transient Simulation and Time-Step Selection
- AC Analysis and Small-Signal Response
- Noise Analysis and Input-Referred Quantities
- Periodic Steady-State and Periodic Noise Analysis
- Parameter Sweeps and Design Exploration
- PVT Corner Simulation
- Monte Carlo Process and Mismatch Analysis
- Convergence Problems and Numerical Artifacts
- Automated Measurements and Specification Checks
- Pre-Layout and Post-Layout Simulation Correlation
8Static CMOS Logic Design12 thèmes
- CMOS Inverter Transfer Characteristics
- Switching Thresholds and Noise Margins
- Inverter Delay and Output Slew
- Pull-Up and Pull-Down Network Construction
- NAND, NOR, and Compound Logic Gates
- AOI and OAI Gate Structures
- Transistor Stacking and Input Ordering
- Gate Sizing for Unequal Loads
- Fanout and Buffer Chain Design
- Logical Effort and Path Sizing
- Short-Circuit and Switching Power
- Leakage-Aware Static Logic Choices
9Alternative Digital Circuit Styles10 thèmes
- Pass-Transistor Logic
- Transmission-Gate Logic
- Multiplexer-Based Circuit Structures
- Ratioed Logic and Static Power Tradeoffs
- Dynamic Precharge and Evaluate Logic
- Domino Logic and Monotonicity Constraints
- Charge Sharing and Charge Leakage
- Keeper Sizing and Noise Robustness
- Dynamic Logic Clocking Requirements
- Logic-Style Selection Under PVT Variation
10Sequential Cells and Clocked Circuits12 thèmes
- Level-Sensitive Latch Circuits
- Edge-Triggered Flip-Flop Structures
- Master-Slave and Pulsed Sequential Elements
- Setup Time, Hold Time, and Clock-to-Q Delay
- Time Borrowing in Latch-Based Designs
- Clock Feedthrough and Internal Node Behavior
- Metastability in Sampling Elements
- Resettable and Settable Cell Variants
- Scan Flip-Flop Circuit Structures
- Integrated Clock-Gating Cells
- Retention and Low-Power Sequential Cells
- Sequential Cell Characterization
11Standard-Cell Layout and Library Development13 thèmes
- Cell Height, Tracks, and Routing Architecture
- Power Rail Placement and Cell Abutment
- Diffusion Sharing and Transistor Ordering
- Pin Accessibility and Routing Congestion
- Well, Tap, and Boundary Cell Requirements
- Drive-Strength and Threshold-Voltage Variants
- Cell-Level DRC and LVS
- Timing Arc Definition and Characterization Grids
- Combinational and Sequential Timing Tables
- Internal Power and Leakage Characterization
- Noise and Waveform Library Models
- Logical, Timing, and Physical View Consistency
- Library Validation and Release Criteria
12Timing, Power, and Area Tradeoffs11 thèmes
- Delay Decomposition into Cell and Wire Components
- Critical Paths and Noncritical Logic
- Switching Activity and Effective Capacitance
- Dynamic, Short-Circuit, and Leakage Power Budgets
- Glitch Power and Unnecessary Transitions
- Voltage, Frequency, and Energy Tradeoffs
- Gate Sizing and Buffer Insertion Tradeoffs
- Logic Depth and Parallelism
- Area Efficiency and Utilization
- Pareto Frontiers for PPA Decisions
- Estimation Accuracy Across Design Stages
Étape 2
RTL & SoC Architecture
RTL, bus, horloges et alimentation
20 modules · 241 thèmes
13RTL Abstraction and Hardware Semantics12 thèmes
- Concurrency in Hardware Description Languages
- Combinational and Sequential Process Models
- Event Scheduling and Simulation Time
- Blocking and Nonblocking Assignment Semantics
- Four-State Logic and Unknown Values
- Bit Width, Signedness, and Expression Evaluation
- Elaboration, Parameters, and Generate Constructs
- Hierarchy, Ports, and Module Connectivity
- Synthesizable and Simulation-Only Constructs
- Simulation and Synthesis Mismatches
- Inferring Hardware from Behavioral Descriptions
- RTL Coding Rules and Review Criteria
14Synthesizable SystemVerilog12 thèmes
- Modules, Packages, and Compilation Units
- Nets, Variables, and Data Types
- Packed and Unpacked Arrays
- Structures, Unions, and Enumerated Types
- always_comb, always_ff, and always_latch
- Functions and Synthesizable Tasks
- Parameterized Modules and Type Parameters
- Interfaces and Modports
- Case Statements and Priority Semantics
- Array Operations and Memory Descriptions
- Compile-Time Assertions and Configuration Checks
- Portable RTL Across Tools and Libraries
15VHDL and Mixed-Language Design10 thèmes
- Entities, Architectures, and Configurations
- Signals, Variables, and Delta Cycles
- Processes and Concurrent Assignments
- Numeric Types and Explicit Conversions
- Generics, Packages, and Reusable Components
- Synthesizable Combinational and Clocked Processes
- Reset and Initialization Semantics
- Verilog and VHDL Boundary Mapping
- Mixed-Language Elaboration and Simulation
- Maintaining Consistent Types and Timing Semantics
16Combinational RTL and Datapath Building Blocks11 thèmes
- Multiplexers, Decoders, and Encoders
- Priority Encoders and Leading-Zero Detection
- Comparators and Magnitude Selection
- Barrel Shifters and Variable Shifts
- Population Count and Reduction Trees
- Lookup Tables and Constant Logic
- Parallel and Iterative Datapath Structures
- Balanced Trees and Critical-Path Reduction
- Avoiding Inferred Latches
- Shared Expressions and Resource Sharing
- Parameterized Combinational Block Verification
17Sequential RTL and Control Logic12 thèmes
- Registers, Enables, and Reset Strategies
- Counters, Timers, and Sequence Generators
- Moore and Mealy State Machines
- State Encoding and Synthesis Implications
- Next-State and Output Logic Organization
- Illegal-State Detection and Recovery
- Handshake Controllers and Backpressure
- Multi-Cycle Operations and Completion Signaling
- Arbitration and Fairness Logic
- Timeouts and Error-State Handling
- Control and Datapath Partitioning
- Reset and Mode-Transition Verification
18Arithmetic Datapath Design13 thèmes
- Fixed-Point Number Representation
- Rounding, Saturation, and Overflow Handling
- Ripple-Carry, Carry-Lookahead, and Prefix Adders
- Carry-Save Arithmetic and Compressor Trees
- Signed Multiplication and Booth Recoding
- Array and Tree Multiplier Architectures
- Multiply-Accumulate Datapaths
- Division and Square-Root Hardware
- CORDIC and Iterative Arithmetic
- Floating-Point Datapath Components
- Precision, Area, and Energy Tradeoffs
- Bit-Accurate Reference Models
- Arithmetic Corner-Case Verification
19Pipelining and Streaming Microarchitecture12 thèmes
- Latency and Initiation Interval
- Pipeline Stage Partitioning
- Register Placement and Retiming Opportunities
- Valid-Ready Streaming Interfaces
- Pipeline Stalls and Bubble Propagation
- Elastic Buffers and Skid Buffers
- Data and Control Alignment
- Pipeline Flush and Cancellation
- Variable-Latency Functional Units
- Throughput Under Backpressure
- Pipeline Power and Clocking Costs
- End-to-End Streaming Correctness
20FIFOs, Queues, and Buffer Microarchitecture11 thèmes
- Circular Buffer Organization
- Read and Write Pointer Management
- Full, Empty, and Almost-Full Detection
- Simultaneous Enqueue and Dequeue Semantics
- Register-Based and SRAM-Based FIFOs
- Queue Depth and Burst Absorption
- Multi-Queue and Shared-Buffer Structures
- Packet Boundaries and Metadata Storage
- Credit Accounting and Buffer Ownership
- Overflow, Underflow, and Recovery Behavior
- Queue Invariants and Boundary-Case Verification
21On-Chip Memory Circuit Design13 thèmes
- SRAM Bitcell Organization
- Read Stability and Write Ability
- Static Noise Margin and Cell Ratios
- Wordline and Bitline Organization
- Precharge and Equalization Circuits
- Sense Amplifiers and Sensing Margins
- Write Drivers and Write-Assist Techniques
- Row and Column Decoders
- Memory Banking and Array Partitioning
- Read and Write Timing Paths
- Low-Voltage Memory Operation
- Memory Variation and Yield Sensitivity
- Register Files, ROMs, and Content-Addressable Memories
22Memory Macro Selection and Integration12 thèmes
- Memory Compiler Inputs and Configuration Choices
- Capacity, Width, Banking, and Port Tradeoffs
- Synchronous and Asynchronous Interface Semantics
- Read-During-Write and Port-Collision Behavior
- Memory Latency and Pipeline Integration
- Macro Timing, Power, and Physical Views
- Memory Power States and Retention
- Byte Enables, Write Masks, and Access Granularity
- Error-Correcting Codes and Parity Integration
- Redundancy and Repair Interface Requirements
- Memory Placement and Routing Constraints
- Macro Model Validation and Integration Checks
23Chip Architecture and Design Partitioning12 thèmes
- Mapping Workloads to Hardware Functions
- Hardware and Software Responsibility Boundaries
- Top-Down Performance and Bandwidth Budgets
- Compute, Storage, and Communication Balance
- Block Partitioning and Interface Contracts
- Clock-Domain and Power-Domain Partitioning
- Shared and Replicated Hardware Resources
- Hierarchical Latency and Power Budgets
- Architectural Performance Models
- Contention and Worst-Case Traffic Scenarios
- Floorplan-Aware Architectural Decisions
- Architecture Review and Design Freeze
24On-Chip Interconnect and Transaction Protocols14 thèmes
- Point-to-Point, Shared-Bus, and Crossbar Structures
- Memory-Mapped and Streaming Transactions
- Request, Response, and Completion Semantics
- AMBA APB, AHB, and AXI Integration Concepts
- Independent Read and Write Channels
- Burst Transfers, Alignment, and Byte Lanes
- Transaction IDs and Response Ordering
- Outstanding Transactions and Backpressure
- Arbitration, Fairness, and Quality of Service
- Protocol Bridges and Width Converters
- Network-on-Chip Routers and Flow Control
- Deadlock Avoidance and Dependency Analysis
- Interconnect Error Responses and Timeouts
- Protocol Compliance Verification
25Register Maps and Peripheral Control Logic11 thèmes
- Address Maps and Register Block Organization
- Read-Only, Read-Write, and Side-Effect Registers
- Write-One-to-Clear and Atomic Register Operations
- Reserved Bits and Forward Compatibility
- Register Access Across Clock Domains
- Interrupt Generation, Masking, and Status Capture
- Timers, Watchdogs, and Event Counters
- DMA Control and Descriptor Interfaces
- Configuration Shadowing and Commit Mechanisms
- Hardware and Firmware Register Contracts
- Register Model and Documentation Generation
26Processor and Subsystem IP Integration12 thèmes
- Selecting Processor IP Against Chip Requirements
- Core Interfaces and Integration Wrappers
- Instruction and Data Memory Connectivity
- Reset Vectors and Boot Address Mapping
- Interrupt Controllers and Event Routing
- Debug and Trace Access Integration
- Cache-Coherent and Noncoherent Interface Boundaries
- DMA Coherency and Shared-Memory Visibility
- Protection Regions and Privilege Signals
- Processor Clock and Power Control Interfaces
- Boot ROM and Minimal Bring-Up Support
- Subsystem Integration Validation
27Application-Specific Accelerators and High-Level Synthesis13 thèmes
- Selecting Kernels for Hardware Acceleration
- Dataflow Graphs and Dependency Analysis
- Compute Array and Processing-Element Organization
- Local Buffers and Data Reuse
- Systolic and Streaming Accelerator Structures
- Precision Selection and Quantization Effects
- Sparse Data and Irregular Workloads
- HLS Scheduling and Resource Binding
- Loop Unrolling, Pipelining, and Memory Partitioning
- HLS Interface Synthesis
- Generated RTL Quality and Physical Feasibility
- Accelerator Control and Host Interface Integration
- Performance Validation Against Reference Workloads
28Clock and Reset Architecture12 thèmes
- Clock Sources and Distribution Requirements
- Primary, Generated, and Divided Clocks
- Clock Multiplexing and Glitch-Free Switching
- Clock Gating and Clock Enable Policies
- Clock Startup, Lock, and Validity Indication
- Reset Sources and Reset Hierarchies
- Synchronous and Asynchronous Reset Choices
- Reset Assertion and Deassertion Sequencing
- Reset During Clock or Power Loss
- Warm Reset and Partial-System Reset
- Test Clocks and Test Reset Overrides
- Clock and Reset Architecture Documentation
29Clock Domain Crossing Design13 thèmes
- Metastability Risk and Synchronizer MTBF
- Single-Bit Synchronizer Structures
- Pulse Transfer and Event Encoding
- Toggle-Based Event Synchronization
- Request-Acknowledge CDC Handshakes
- Multi-Bit Data Coherency
- Gray-Code Counters and Pointer Transfer
- Asynchronous FIFO Architecture
- Reconvergence and Correlated Control Signals
- Clock-Ratio and Clock-Stoppage Assumptions
- Synchronizer Placement and Timing Constraints
- Structural and Functional CDC Analysis
- CDC Waiver Justification and Closure
30Reset Domain Crossing and Initialization10 thèmes
- Reset Domains Within Shared Clock Domains
- Asynchronous Reset Release Hazards
- Reset-Induced Data and Control Transitions
- Interactions Between Reset Synchronizers and CDC Logic
- Partial Reset of Communicating Blocks
- Reset Sequencing Across Power Domains
- Memory Initialization and Uninitialized State
- Unknown-Value Propagation During Startup
- Reset Domain Crossing Analysis
- Reset Convergence and Startup Assertions
31Low-Power Chip Architecture13 thèmes
- Workload-Based Power-State Definition
- Coarse and Fine-Grained Clock Gating
- Operand Isolation and Activity Suppression
- Power Gating and Domain Partitioning
- Retained and Nonretained State Selection
- Multi-Voltage Architectures
- Dynamic Voltage and Frequency Scaling
- Always-On Control and Wakeup Sources
- Sleep Entry and Wakeup Latency Budgets
- Memory Sleep and Retention Modes
- Inrush Current and Staged Power Restoration
- Power Management State Machines
- Energy Break-Even Analysis for Power States
32Power Intent and Low-Power Verification13 thèmes
- UPF Design Hierarchy and Power Domains
- Supply Ports, Nets, and Supply Sets
- Power States and Legal State Transitions
- Isolation Strategies and Clamp Values
- Level-Shifter Strategies and Placement Intent
- Retention Strategies and Save-Restore Controls
- Power Switch Definition and Control
- Always-On Logic Requirements
- Power-Aware Simulation and State Corruption
- Static Power-Intent Consistency Checks
- Low-Power Assertions and Coverage
- Power Intent Refinement Through Implementation
- Verification of Power Sequencing and Recovery
Étape 3
Functional & Formal Verification
La preuve que ça marche avant d'être fabriqué
8 modules · 95 thèmes
33Verification Planning and Testbench Foundations12 thèmes
- Verification Plans Derived from Requirements
- Block, Subsystem, and Full-Chip Verification Scope
- Directed, Random, Formal, and Emulation Strategies
- Stimulus Generation and DUT Interfaces
- Drivers, Monitors, and Transaction Models
- Reference Models and Golden Results
- Scoreboards and End-to-End Checking
- Clock and Reset Generation in Testbenches
- Positive, Negative, and Stress Scenarios
- Reproducible Seeds and Configuration Tracking
- Bug Severity and Verification Exit Criteria
- Independence Between Design and Checking Logic
34SystemVerilog for Functional Verification11 thèmes
- Classes, Inheritance, and Polymorphism
- Random Variables and Constraint Solving
- Constraint Distribution and Scenario Biasing
- Queues, Mailboxes, and Dynamic Data Structures
- Events, Semaphores, and Process Synchronization
- Clocking Blocks and Race Avoidance
- Virtual Interfaces and Testbench Connectivity
- Functional Coverage Groups and Sampling
- DPI Integration with Reference Models
- Testbench Configuration and Object Lifetimes
- Constrained-Random Stimulus Debugging
35Universal Verification Methodology14 thèmes
- UVM Component Hierarchy and Test Structure
- Build, Connect, and Run Phases
- Sequence Items and Transaction Abstraction
- Sequences, Sequencers, and Drivers
- Active and Passive Agents
- Monitors and Analysis Connections
- Scoreboards, Predictors, and Subscribers
- Factory Overrides and Reusable Components
- Configuration Database and Resource Management
- Objections and End-of-Test Control
- Register Abstraction Layer Models
- Virtual Sequences and System-Level Coordination
- UVM Reporting and Debug Practices
- Verification IP Integration and Reuse
36Assertions and Protocol Checking11 thèmes
- Immediate and Concurrent Assertions
- Sequences, Properties, and Temporal Operators
- Sampling Semantics and Clocked Properties
- Implication and Overlapping Behavior
- Reset Disabling and Assertion Activation
- Safety and Liveness Properties
- Handshake, Ordering, and Stability Checks
- FIFO Occupancy and Credit Invariants
- Latency-Bounded Response Properties
- Assertion Vacuity and Unreachable Antecedents
- Assertion Coverage and Reusable Checkers
37Formal Property Verification12 thèmes
- State-Space Models and Formal Proof Objectives
- Assumptions, Assertions, and Cover Properties
- Bounded Model Checking and Inductive Proof
- Reachability and Counterexample Analysis
- Environmental Constraints and Overconstraint Risks
- Abstraction and State-Space Reduction
- Cutpoints and Assume-Guarantee Reasoning
- Formal Analysis of Arbitration and Queues
- Deadlock, Livelock, and Forward Progress
- Arithmetic and Datapath Property Checking
- Proof Convergence and Inconclusive Results
- Formal Signoff Evidence and Limitations
38Coverage Closure and Verification Debug12 thèmes
- Code, Functional, and Assertion Coverage
- Coverage Crosses and Scenario Explosion
- Exclusions and Unreachable Coverage Targets
- Coverage Gaps and Directed Test Creation
- Regression Selection and Test Prioritization
- Simulation Failure Triage
- Waveform, Transaction, and Log-Based Debugging
- Nondeterministic Testbench Failures
- X-Optimism and X-Pessimism Analysis
- Bug Reproduction and Minimal Failing Cases
- Coverage Trends and Closure Reporting
- Verification Results Linked to Requirements
39Subsystem and Full-Chip Verification13 thèmes
- Hierarchical Verification Environment Reuse
- Multi-Master Traffic and Resource Contention
- End-to-End Data Integrity Checks
- Memory Map and Connectivity Verification
- Interrupt and Error Propagation Scenarios
- Concurrent Clock, Reset, and Power Events
- Hardware-Software Co-Verification Interfaces
- Boot and Initialization Scenario Testing
- Performance Counters and Bandwidth Validation
- Security and Protection Boundary Checks
- Mixed-Signal Behavioral Model Integration
- Gate-Level Simulation and SDF Annotation
- Full-Chip Verification Readiness Reviews
40Emulation and FPGA Prototyping for ASIC Validation10 thèmes
- Choosing Simulation, Emulation, or Prototyping
- Partitioning Large Designs for Hardware Execution
- ASIC Clock and Memory Mapping to Prototype Resources
- Transactors and Transaction-Level Interfaces
- Synthesizable Test Harnesses
- Prototype Timing and Functional Equivalence Limits
- Long-Running Workload and Software Validation
- Internal Visibility and Trace Capture
- Reproducing Prototype Failures in Simulation
- Correlating Prototype Results with ASIC Constraints
Étape 4
Synthesis, Timing & Physical Design
Du netlist à un layout prêt pour signoff
13 modules · 157 thèmes
41Logic Synthesis and Technology Mapping12 thèmes
- RTL Elaboration and Design Linking
- Library Selection and Operating Conditions
- Logic Optimization and Boolean Factoring
- Arithmetic Inference and Resource Mapping
- Sequential Optimization and Register Retiming
- Technology Mapping to Standard Cells
- Clock-Gating Inference and Insertion
- Area, Timing, and Power Optimization Priorities
- Physical-Aware Synthesis
- Hierarchical and Incremental Synthesis
- Unmapped Logic and Inference Diagnostics
- Synthesis Reports and Netlist Quality Review
42Equivalence Checking and Structural Design Quality11 thèmes
- RTL-to-RTL and RTL-to-Netlist Equivalence
- Combinational and Sequential Equivalence
- State Mapping and Register Correspondence
- Handling Black Boxes and Memory Models
- Reset, Initialization, and Unknown-State Assumptions
- Equivalence Across Retiming and Low-Power Changes
- Counterexample Diagnosis in Equivalence Failures
- Undriven, Multiply Driven, and Floating Nets
- Combinational Loops and Unintended Storage
- Lint Rules, Exceptions, and Signoff Records
- Netlist Sanity and Hierarchy Consistency Checks
43Timing Constraints and Constraint Validation13 thèmes
- Defining Primary and Generated Clocks
- Clock Period, Waveform, and Uncertainty
- Source and Network Latency Modeling
- Input and Output Delay Constraints
- Input Transition and Output Load Modeling
- Clock Groups and Asynchronous Relationships
- False Paths and Their Functional Justification
- Multicycle Paths and Paired Setup-Hold Constraints
- Maximum and Minimum Delay Constraints
- Case Analysis and Mode-Specific Constraints
- Clock-Gating and Recovery-Removal Checks
- Unconstrained Path Detection
- Constraint Consistency Across Hierarchical Flows
44Static Timing Analysis Fundamentals12 thèmes
- Timing Graphs, Startpoints, and Endpoints
- Arrival Time, Required Time, and Slack
- Setup and Hold Path Analysis
- Cell Delay and Slew Propagation
- Interconnect Delay and Effective Load
- Launch and Capture Clock Relationships
- Clock Skew and Timing Budgets
- Timing Through Latches and Transparent Paths
- Recovery, Removal, and Minimum Pulse Width
- Maximum Transition, Capacitance, and Fanout Checks
- Reading and Debugging Timing Reports
- Distinguishing Constraint Errors from Design Failures
45Advanced Timing Analysis and Variation12 thèmes
- Multi-Mode Multi-Corner Analysis
- On-Chip Variation and Timing Derates
- Advanced and Parametric Variation Models
- Common Clock Path Pessimism Removal
- Graph-Based and Path-Based Analysis
- Crosstalk-Aware Timing Analysis
- Voltage and Temperature Effects on Critical Paths
- Timing Models for Hierarchical Blocks
- Interface Budgeting and Boundary Constraints
- Statistical Variation and Timing Margin Choices
- Clock Jitter Allocation and Correlation
- Signoff Scenario Selection and Coverage
46Floorplanning and Physical Hierarchy12 thèmes
- Die Size, Core Area, and Utilization Planning
- Aspect Ratio and Routing Resource Tradeoffs
- Macro Placement and Orientation
- Pin Placement and Interface Locality
- Placement Halos, Channels, and Blockages
- Standard-Cell Rows and Placement Sites
- Voltage Areas and Power-Domain Boundaries
- Analog and Digital Region Separation
- Hierarchical Blocks and Physical Partitions
- Feedthrough Planning and Long-Distance Connectivity
- Early Congestion and Timing Estimation
- Floorplan Feasibility Reviews
47Power Distribution Network Implementation12 thèmes
- Chip-Level Current Budgets and Power Maps
- Power Rings, Straps, and Standard-Cell Rails
- Power Grid Layer and Width Selection
- Via Arrays and Power Connectivity
- Multiple Supply Nets and Domain Isolation
- Power Switch Placement and Distribution
- Always-On Supply Routing
- Decoupling Capacitance Planning
- Macro and Analog Supply Connections
- Package Supply Entry Points as Design Constraints
- Power Grid Connectivity Verification
- Early IR-Drop and Current-Density Assessment
48Placement and Physical Optimization12 thèmes
- Global and Detailed Placement
- Timing-Driven and Congestion-Driven Placement
- Density Targets and Local Hotspots
- Legalization and Cell Orientation Rules
- Buffering and High-Fanout Net Optimization
- Gate Resizing and Threshold-Voltage Swapping
- Register Clustering and Multi-Bit Flip-Flops
- Macro Boundary and Pin-Access Challenges
- Physical Optimization of Critical Datapaths
- Placement Constraints for Synchronizers
- Scan Chain Reordering During Placement
- Placement Quality Metrics and Checkpoints
49Clock Tree Synthesis and Distribution12 thèmes
- Clock Tree Topologies and Distribution Styles
- Clock Buffer and Inverter Selection
- Skew, Latency, Slew, and Clock Power Targets
- Clock Sink Clustering and Balancing
- Useful Skew and Timing Optimization
- Clock Gating Placement and Cloning
- Clock Routing Layers and Shielding
- Multiple Clock Modes and Generated Clock Handling
- Clock Mesh and Hybrid Distribution Concepts
- Post-CTS Setup and Hold Repair
- Clock Tree Variation and Robustness
- Clock Distribution Signoff Checks
50Routing and Parasitic Extraction13 thèmes
- Global Routing and Congestion Estimation
- Detailed Routing and Track Assignment
- Routing Layer Constraints and Preferred Directions
- Via Selection and Via Count Tradeoffs
- Pin Access and Routing Detours
- Nondefault Rules for Sensitive Nets
- Shielding and Spacing Strategies
- Antenna Violation Detection and Repair
- Metal Fill and Parasitic Effects
- Resistance and Capacitance Extraction
- Coupling Capacitance and Extraction Corners
- SPEF Generation and Netlist Annotation
- Extraction Accuracy and Runtime Tradeoffs
51Signal and Power Integrity Analysis12 thèmes
- Crosstalk Aggressors and Victims
- Noise Glitches and Functional Noise Margins
- Coupling-Induced Delay Changes
- Simultaneous Switching Noise
- Static and Dynamic IR Drop
- Power Grid Resonance and Supply Impedance
- Activity-Based Power Integrity Scenarios
- Electromigration Limits in Wires and Vias
- Local Supply Droop and Timing Interaction
- Decoupling, Buffering, and Routing Remedies
- Package Models in Chip-Level Integrity Analysis
- Correlating Integrity Failures with Physical Locations
52Physical Verification and Layout Signoff12 thèmes
- Design Rule Checking and Rule Categories
- Layout Versus Schematic Comparison
- Device Recognition and Netlist Extraction
- Electrical Rule Checking
- Well, Substrate, and Tap Connectivity Checks
- Density and Metal Fill Verification
- Antenna Rule Signoff
- Voltage-Aware and Reliability-Oriented Layout Checks
- Hierarchical Verification and Black-Box Handling
- Debugging Shorts, Opens, and Parameter Mismatches
- Waiver Review and Exception Documentation
- Final Layout and Schematic Consistency
53Design Closure and Engineering Change Orders12 thèmes
- Prioritizing Timing, Power, and Area Violations
- Setup Repair and Critical-Path Restructuring
- Hold Repair and Minimum-Delay Control
- Congestion Repair and Local Placement Changes
- Power Recovery After Timing Closure
- Functional and Timing ECO Workflows
- Spare Cells and Metal-Only ECO Planning
- ECO Netlist and Layout Synchronization
- Incremental Extraction and Signoff Rechecks
- Equivalence Verification After ECOs
- Multi-Corner Regression Following Changes
- Closure Criteria and Residual Risk Tracking
Étape 5
Analog & Mixed-Signal
Où les puces rencontrent le monde réel
16 modules · 192 thèmes
54Analog IC Design Methodology12 thèmes
- Translating Analog Specifications into Circuit Budgets
- Gain, Bandwidth, Linearity, Noise, and Power Tradeoffs
- Topology Selection Under Supply Constraints
- Transistor Sizing with gm/ID Methods
- Inversion Level and Current Density Selection
- Device Lookup Tables from PDK Models
- Intrinsic Gain and Speed Limitations
- Bias Headroom and Signal Swing Allocation
- Sensitivity Analysis and Design Margins
- PVT-Robust Design and Statistical Yield
- Schematic-to-Layout Iteration Planning
- Analog Design Review Documentation
55Bias Circuits and Voltage References12 thèmes
- Simple, Cascode, and Regulated Current Mirrors
- Current Mirror Accuracy and Compliance
- Bias Distribution and Loading Effects
- Self-Biased Circuits and Startup Paths
- PTAT and CTAT Reference Components
- Bandgap Reference Architectures
- Sub-Bandgap and Low-Voltage References
- Supply Rejection and Line Sensitivity
- Temperature Curvature and Compensation
- Trimming and Reference Calibration
- Reference Noise and Filtering
- Startup and Abnormal Supply Conditions
56Integrated Amplifiers and Operational Transconductance Amplifiers13 thèmes
- Differential Input Stage Design
- Active Loads and Gain Enhancement
- Telescopic and Folded-Cascode OTAs
- Two-Stage and Multistage Amplifiers
- Gain Boosting and Auxiliary Amplifier Design
- Frequency Compensation and Loop Stability
- Slew Rate and Large-Signal Settling
- Fully Differential Architectures
- Common-Mode Feedback Circuits
- Output Stage and Load-Driving Design
- Rail-to-Rail Input and Output Constraints
- Unity-Gain, Closed-Loop, and Transient Verification
- PVT and Load-Dependent Stability Analysis
57Noise, Offset, and Precision Analog Design12 thèmes
- Thermal and Flicker Noise Contributions
- Noise Budgeting Across Analog Stages
- Device Area, Bias Current, and Noise Tradeoffs
- Input-Referred Offset and Mismatch
- Random and Systematic Error Separation
- Chopper Stabilization
- Auto-Zeroing and Correlated Double Sampling
- Noise Folding and Sampling Effects
- Common-Mode and Power-Supply Rejection
- Precision Error Budgets and Drift
- Monte Carlo Analysis of Precision Metrics
- Calibration Range and Residual Error
58Analog Switches and Sampled-Data Circuits12 thèmes
- MOS Sampling Switch Resistance
- Signal-Dependent Switch Nonlinearity
- Transmission-Gate Sampling Networks
- Bootstrapped Switch Design Constraints
- Charge Injection and Clock Feedthrough
- Track-and-Hold and Sample-and-Hold Circuits
- Sampling Capacitor Sizing and kT/C Noise
- Acquisition Time and Settling Error
- Bottom-Plate Sampling
- Nonoverlapping Clock Generation
- Switched-Capacitor Charge Transfer
- Leakage, Droop, and Hold-Time Limits
59Comparator Circuit Design10 thèmes
- Static and Dynamic Comparator Architectures
- Regenerative Latches and Decision Time
- Preamplifier and Latch Partitioning
- Input-Referred Comparator Offset
- Comparator Noise and Decision Uncertainty
- Kickback Noise and Input Isolation
- Metastability and Near-Threshold Decisions
- Hysteresis and Noise Immunity
- Comparator Calibration and Offset Cancellation
- Clocking, Reset, and PVT Robustness
60Analog-to-Digital Converter Design14 thèmes
- ADC Resolution, Sample Rate, and Conversion Latency
- Quantization, DNL, and INL
- SNR, SINAD, ENOB, and SFDR
- Flash ADC Encoding and Comparator Arrays
- SAR ADC Architecture and Bit Cycling
- Capacitive DACs Within SAR Converters
- Pipelined ADC Stages and Residue Amplification
- Redundancy and Digital Error Correction
- Oversampling and Delta-Sigma Modulation
- Discrete-Time and Continuous-Time Modulators
- Decimation Interface and Out-of-Band Noise
- Time-Interleaved ADCs and Channel Mismatch
- Reference Loading and Sampling Clock Jitter
- ADC Calibration and Behavioral Verification
61Digital-to-Analog Converter Design11 thèmes
- DAC Resolution, Linearity, and Settling Specifications
- Resistor-String and R-2R Architectures
- Current-Steering DAC Architectures
- Binary, Unary, and Segmented Coding
- Capacitive DAC Structures
- Element Matching and Gradient Sensitivity
- Switching Glitches and Dynamic Linearity
- Output Compliance and Load Effects
- Dynamic Element Matching
- DAC Calibration and Trimming
- Spectral and Transient DAC Characterization
62Integrated Analog Filters10 thèmes
- On-Chip Filter Specifications and Error Budgets
- Active-RC Filter Architectures
- Transconductance-Capacitor Filters
- Switched-Capacitor Filter Structures
- Biquad Realization and Cascading
- Noise, Linearity, and Dynamic Range Allocation
- Frequency Tuning and Process Variation
- Clock Feedthrough in Sampled Filters
- Anti-Alias and Reconstruction Filter Integration
- Filter Stability and PVT Verification
63PLLs, DLLs, and On-Chip Clock Generation13 thèmes
- Ring Oscillator and Controlled Oscillator Design
- PLL Architecture and Frequency Synthesis
- Phase-Frequency Detectors and Charge Pumps
- Loop Filters and Stability Tradeoffs
- Feedback Dividers and Prescalers
- Integer-N and Fractional-N Operation
- Jitter, Phase Noise, and Reference Spurs
- Lock Acquisition and Frequency Calibration
- Delay-Locked Loops and Delay Lines
- Digitally Controlled Oscillators and Digital PLLs
- Supply and Substrate Noise Sensitivity
- Clock Generation Behavioral Models
- PLL and DLL Verification Across Operating Modes
64On-Chip Power Management Circuits12 thèmes
- LDO Regulator Architectures
- Error Amplifiers and Pass-Device Sizing
- LDO Stability and Output-Capacitance Constraints
- Load Transient Response and Dropout Voltage
- Quiescent Current and Power-Supply Rejection
- Charge Pumps and Switched-Capacitor Regulators
- Integrated Power Switches and Gate Drivers
- Soft Start and Supply Sequencing Circuits
- Brownout Detection and Supply Monitors
- Current Limiting and Thermal Protection Interfaces
- Interaction Between Regulators and Digital Loads
- Power Management Circuit Verification
65Analog and Custom Layout13 thèmes
- Matching-Oriented Device Placement
- Common-Centroid and Interdigitated Structures
- Dummy Devices and Edge-Effect Control
- Orientation, Stress, and Well-Proximity Effects
- Symmetry in Differential Signal Paths
- Guard Rings and Substrate Isolation
- Sensitive Node Routing and Shielding
- Analog Power and Ground Distribution
- Resistor and Capacitor Array Layout
- Parasitic Balancing and Critical Node Capacitance
- Layout-Dependent Effects in Extracted Simulation
- Analog DRC, LVS, and Electrical Checks
- Post-Layout Performance Recovery
66Mixed-Signal Modeling and Verification12 thèmes
- Behavioral Abstraction for Analog Blocks
- Verilog-A and Verilog-AMS Modeling
- Real-Number Models for Digital Simulation
- Electrical and Discrete-Event Domain Interfaces
- Connect Modules and Signal Discipline Boundaries
- Modeling Quantization, Saturation, and Nonlinearity
- Modeling Noise, Jitter, and Statistical Variation
- Model Accuracy and Simulation Performance Tradeoffs
- Correlation Between Behavioral and Transistor Models
- Mixed-Signal Assertions and Measurement Monitors
- Analog-Digital Co-Simulation Debugging
- Mixed-Signal Regression Coverage
67Mixed-Signal SoC Integration and Calibration12 thèmes
- Analog and Digital Partitioning at Chip Level
- Clock, Reference, and Supply Distribution Budgets
- Substrate Coupling and Isolation Strategy
- Digital Activity Scheduling Around Sensitive Measurements
- Analog Configuration Registers and Control Interfaces
- Startup Ordering of References, Clocks, and Converters
- Foreground and Background Calibration
- Calibration State Machines and Convergence
- Trim Storage and Calibration Data Integrity
- Analog Test Modes and Digital Observability
- Full-Chip Mixed-Signal Error Budgets
- Cross-Domain Failure Diagnosis
68I/O Cells, Pad Rings, and Protection Integration12 thèmes
- I/O Voltage Standards and Electrical Requirements
- Input Buffers and Output Driver Structures
- Bidirectional Pads and Output-Enable Control
- Drive Strength, Slew Rate, and Loading
- Level Translation at Chip Boundaries
- Fail-Safe and Power-Off I/O Behavior
- Pad Ring Organization and Supply Segmentation
- ESD Protection Network Integration
- Latch-Up Prevention Through Layout Constraints
- Bond Pad and Bump Connectivity Planning
- Pad-Level Test Access and Boundary Scan
- I/O Library Verification and Signoff Interfaces
69High-Speed Wireline Interface Circuits12 thèmes
- Serializer and Deserializer Architecture
- Transmitter Drivers and Output Equalization
- Receiver Front Ends and Input Termination
- Continuous-Time and Decision-Feedback Equalization
- Clock and Data Recovery Concepts
- Source-Synchronous and Embedded-Clock Interfaces
- Jitter Budgets and Timing Margins
- Eye Diagrams and Bit Error Measurements
- Channel Models as PHY Design Inputs
- Parallel Memory PHY Timing and Training
- On-Chip Loopback and Built-In Link Test
- PHY Macro Integration and Mixed-Signal Verification
Étape 6
Test, Tape-Out & Silicon
DFT, tape-out et premier silicium
15 modules · 181 thèmes
70Design-for-Test Architecture12 thèmes
- Manufacturing Defects and Logical Fault Models
- Controllability and Observability
- Structural Test and Functional Test Objectives
- DFT Requirements During Chip Architecture
- Test Modes and Normal-Mode Isolation
- Test Clock, Reset, and Power Requirements
- Hierarchical DFT Partitioning
- Test Access, Pin Budget, and Test Time
- Logic, Memory, and Analog Test Strategy
- DFT Impact on Timing, Area, and Power
- Test Coverage Targets and Untestable Logic
- DFT Specification and Integration Reviews
71Scan Design and Automatic Test Pattern Generation13 thèmes
- Scan Insertion and Scan Cell Selection
- Scan Chain Partitioning and Balancing
- Scan Enable Distribution and Timing
- Lockup Latches and Clock-Domain Boundaries
- Scan Compression and Response Compaction
- Stuck-At and Transition Fault ATPG
- Path-Delay and Cell-Aware Test Concepts
- At-Speed Launch and Capture Schemes
- Unknown Sources and X-Masking
- Test Power and Shift-Capture Constraints
- Fault Simulation and Coverage Analysis
- Pattern Simulation and DFT Rule Checking
- Scan Chain Diagnosis and Failure Localization
72Memory Built-In Self-Test and Repair12 thèmes
- Memory Fault Models and Test Objectives
- March Algorithms and Address Sequencing
- MBIST Controller Architecture
- Shared and Distributed Memory Test Controllers
- Test Data Backgrounds and Coupling Fault Coverage
- Memory Test Scheduling and Power Limits
- Built-In Redundancy Analysis
- Spare Rows, Spare Columns, and Repair Allocation
- Fuse and Nonvolatile Repair Data Interfaces
- Repair Loading and Post-Repair Verification
- Memory Diagnostics and Failure Maps
- MBIST Integration Across Clock and Power Domains
73Analog and Mixed-Signal Test Design11 thèmes
- Analog Test Access and Multiplexing
- Measurement Loading and Test Path Parasitics
- DC Parametric Test Structures
- ADC Static and Dynamic Test Methods
- DAC Linearity and Settling Measurements
- PLL Lock, Jitter, and Frequency Measurements
- Analog Loopback and Built-In Self-Test
- On-Chip Monitors and Measurement Circuits
- Trim and Calibration Test Sequences
- Test Correlation Between Bench and Production
- Analog Test Time and Coverage Tradeoffs
74Chip Test Interfaces and Production Test Handoff12 thèmes
- JTAG Test Access Ports and Boundary Scan
- Embedded Instrument Access Networks
- Test Wrappers and Hierarchical Access
- Test Pattern Formats and Tester Constraints
- Wafer Probe and Packaged-Part Test Interfaces
- Test Pin Assignment and Contact Limitations
- DC, Functional, and Structural Test Content
- Test Limits, Guardbands, and Measurement Variation
- Shmoo Plots and Operating-Window Characterization
- Speed and Power Binning Inputs
- Tester Correlation and Pattern Debug Handoff
- Production Test Documentation and Revision Control
75Reliability and Robust Circuit Design12 thèmes
- Design Mission Profiles and Stress Conditions
- Bias Temperature Instability and Aging Models
- Hot-Carrier Degradation and Timing Drift
- Dielectric Stress and Voltage Reliability Limits
- Electromigration-Aware Circuit and Layout Choices
- Self-Heating and Temperature Gradients
- Soft Errors and Transient Fault Sensitivity
- Redundancy, Parity, and Error Correction Tradeoffs
- Derating and End-of-Life Design Margins
- Aging-Aware Timing and Analog Verification
- Robust Startup and Abnormal-State Recovery
- Reliability Evidence for Design Release
76Hardware Safety and Security Features13 thèmes
- Safety and Security Requirements at Chip Boundaries
- Fault Containment and Error Reporting
- Lockstep, Redundancy, and Consistency Checking
- Diagnostic Coverage and Fault Injection Models
- Watchdogs and Clock-Supply Monitoring
- Hardware Root-of-Trust Integration
- Boot Authentication and Lifecycle State Interfaces
- Secure Storage and Key Access Boundaries
- Debug Authorization and Test Access Restrictions
- Side-Channel-Aware Design Tradeoffs
- Fault-Injection Resistance at the Circuit Interface
- Security Properties and Information-Flow Checks
- Fail-Safe States and Recovery Verification
77Advanced-Node Implementation Constraints12 thèmes
- Device Geometry Constraints in FinFET and GAA Libraries
- Quantized Sizing and Cell Architecture Choices
- Restricted Design Rules and Layout Regularity
- Pin Density and Local Routing Limits
- Local Interconnect Resistance and Via Bottlenecks
- Patterning Constraints as Layout Design Inputs
- Variation and Margin Management at Low Voltages
- Advanced Clock and Power Distribution Challenges
- Backside Power Delivery Design Interfaces
- Thermal Density and Placement Tradeoffs
- Design-Technology Co-Optimization Concepts
- Porting IP Between Technology Generations
78Chiplets and Three-Dimensional IC Design Interfaces13 thèmes
- Monolithic and Multi-Die Architecture Tradeoffs
- Functional Partitioning Across Dies
- Die-to-Die Bandwidth, Latency, and Energy Budgets
- Chiplet Protocol and PHY Compatibility
- Die-to-Die Clocking and Synchronization
- Bump Maps and Inter-Die Connectivity Contracts
- Power Delivery and Cross-Die Thermal Constraints
- Hierarchical Timing and Power Models
- Cross-Die Test, Debug, and Observability
- Known-Good-Die Requirements and Test Strategy
- Multi-Die Reset, Boot, and Fault Handling
- Chiplet Model Exchange and Integration Verification
- Design Handoff to Packaging and Assembly Teams
79IP Reuse, Qualification, and Delivery12 thèmes
- Soft, Firm, and Hard IP Deliverables
- IP Selection Against Functional and Physical Requirements
- Configuration Parameters and Supported Use Cases
- IP Integration Guides and Interface Contracts
- Verification Evidence and Coverage Reports
- Timing, Power, and Physical Model Qualification
- IP Clock, Reset, and Power Assumptions
- Third-Party IP Errata and Change Tracking
- Version Compatibility and Dependency Management
- Reusable Register and Interface Descriptions
- IP Packaging, Licensing Constraints, and Provenance
- Acceptance Criteria for Internal IP Releases
80Design Automation and Reproducible Engineering12 thèmes
- Tcl Automation for EDA Tool Flows
- Python for Report Parsing and Design Analysis
- Parameterized Run Configuration
- Dependency Tracking Across Design Stages
- Version Control for RTL, Constraints, and Scripts
- Reproducible Tool and Library Environments
- Automated Lint, Simulation, and Formal Regressions
- Batch Job Management and Compute Resource Planning
- Design Metrics Collection and Comparison
- Run Failure Detection and Recovery
- Artifact Naming, Checksums, and Traceability
- Release Baselines and Archived Design Evidence
81Tape-Out Preparation and Design Release13 thèmes
- Tape-Out Readiness Planning
- Final Functional and Verification Signoff
- Final Timing, Power, and Integrity Signoff
- Physical Verification Completion
- DFT and Test Pattern Readiness
- Final Netlist, Layout, and Model Consistency
- Foundry Submission Requirements and Deliverable Checks
- Layer Mapping, Top Cells, and Layout Database Integrity
- Seal Ring, Pad, and Scribe Interface Requirements
- IP, PDK, and Tool Version Freeze
- Waivers, Known Issues, and Risk Acceptance Records
- Release Manifest and Approval Traceability
- Handoff to Fabrication, Packaging, and Test Teams
82First-Silicon Bring-Up and Characterization12 thèmes
- Bring-Up Plans Derived from Chip Specifications
- Evaluation Hardware and Instrumentation Requirements
- Supply Sequencing and Initial Current Checks
- Clock, Reset, and Basic Connectivity Validation
- JTAG Access and On-Chip Debug Activation
- Boot and Minimal Functional Execution
- Memory, Interconnect, and Peripheral Validation
- Analog Block Startup and Calibration
- Voltage, Frequency, and Temperature Characterization
- Power and Performance Measurement
- Simulation-to-Silicon Correlation
- Characterization Results and Design Margin Assessment
83Silicon Debug, Diagnosis, and Design Revisions12 thèmes
- Distinguishing Design, Test, and Manufacturing Failures
- Failure Reproduction and Controlled Experiments
- Register, Trace, and Scan-Based Debug
- Signature Analysis and Failure Localization
- Timing-Sensitive and Intermittent Failures
- Power, Reset, and Clock Interaction Failures
- Analog Outliers and Calibration Failures
- Yield Data as Feedback to Design Teams
- Model Gaps and Correlation Error Analysis
- Workarounds, Metal Fixes, and Full Respin Decisions
- Root-Cause Documentation and Corrective Actions
- Feeding Silicon Findings into Reusable Design Rules
84Chip Development Cost, Schedule, and Risk10 thèmes
- Die Area and Design Cost Drivers
- Engineering Effort, IP Cost, and Tool Resources
- Prototype, Shuttle, and Dedicated Tape-Out Choices
- Yield Assumptions in Architecture Decisions
- Verification Effort and Late-Change Risk
- Build-versus-License Decisions for IP
- Schedule Dependencies and Critical Design Milestones
- Cost of Testability and Debug Features
- Respin Contingency and Risk Reduction
- Technical Trade Studies and Design Decision Records
Étape 7
Practicum & Capstone
Votre propre bloc, du cahier des charges au signoff
5 modules · 53 thèmes
85Digital Block Design Practicum10 thèmes
- Writing a Parameterized Hardware Block Specification
- Building a Bit-Accurate Reference Model
- Designing Control and Datapath Microarchitecture
- Implementing Synthesizable RTL
- Creating a Self-Checking Testbench
- Writing Protocol and Data Integrity Assertions
- Exercising Backpressure, Reset, and Error Scenarios
- Reviewing Lint, Coverage, and Formal Results
- Synthesizing and Comparing Architecture Variants
- Delivering a Reusable and Documented IP Block
86RTL-to-Layout Implementation Practicum11 thèmes
- Selecting a Supported PDK and Cell Library
- Preparing Timing and Power Constraints
- Running Synthesis and Equivalence Checks
- Creating a Floorplan and Power Grid
- Performing Placement and Clock Tree Synthesis
- Routing and Extracting Parasitics
- Analyzing Multi-Corner Timing
- Repairing Setup, Hold, and Routing Violations
- Running DRC, LVS, and Connectivity Checks
- Comparing Pre-Layout and Post-Layout PPA
- Preparing an Auditable Implementation Report
87Analog and Mixed-Signal Design Practicum10 thèmes
- Allocating Specifications for an Analog Signal Path
- Selecting and Sizing a Circuit Topology
- Characterizing Bias, Gain, Noise, and Linearity
- Running PVT and Statistical Simulations
- Creating a Correlated Behavioral Model
- Developing Matching-Aware Custom Layout
- Completing Extraction and Post-Layout Verification
- Integrating Digital Configuration and Calibration
- Evaluating Startup and Supply Disturbance Behavior
- Preparing a Mixed-Signal Verification Report
88Verification and DFT Integration Practicum10 thèmes
- Building a Requirement-Based Verification Plan
- Assembling Reusable Verification Components
- Combining Simulation, Assertions, and Formal Checks
- Verifying CDC, Reset, and Power-State Transitions
- Closing Functional and Structural Coverage Gaps
- Defining Scan and Memory Test Architecture
- Checking Test Mode Isolation and Clocking
- Evaluating Fault Coverage and Test Power
- Validating Test Access and Debug Features
- Producing Verification and DFT Signoff Evidence
89Integrated Chip Design Capstone12 thèmes
- Selecting a Feasible Chip Application and Scope
- Defining Architecture and Measurable Acceptance Criteria
- Allocating Area, Timing, Power, and Interface Budgets
- Developing or Integrating Digital and Mixed-Signal IP
- Maintaining Requirements and Configuration Traceability
- Executing Block and System Verification
- Completing Physical Implementation and Design Closure
- Integrating Test, Debug, and Calibration Support
- Preparing a Tape-Out-Style Release Package
- Writing a First-Silicon Bring-Up and Characterization Plan
- Reviewing Design Risks and Unresolved Limitations
- Presenting Design Evidence and Engineering Tradeoffs
Quinze minutes.Chaque jour.
- 1
Une leçon tient dans une pause déjeuner
Une idée à la fois, en diapositives courtes. Une leçon entière prend environ quinze minutes.
- 2
Des exercices corrigés à l'instant
Les questions sont dans la leçon. Répondez et voyez tout de suite si c'est juste.
- 3
Une série qui donne envie de revenir
Une leçon par jour entretient la série. De petites séances régulières vous mènent au bout.
- 1
Une leçon tient dans une pause déjeuner
Une idée à la fois, en diapositives courtes. Une leçon entière prend environ quinze minutes.
- 2
Des exercices corrigés à l'instant
Les questions sont dans la leçon. Répondez et voyez tout de suite si c'est juste.
- 3
Une série qui donne envie de revenir
Une leçon par jour entretient la série. De petites séances régulières vous mènent au bout.
Votre place dans une équipe de tape-out.
Développeurs FPGA qui passent à l'ASIC
Là où vous progresserez le plus
Bouclez le timing du floorplan au signoff
Étape 4 · Synthesis, Timing & Physical DesignDiplômés en électronique, numérique ou analogique
Développeurs logiciels attirés par le matériel
Là où vous progresserez le plus
Écrivez du RTL synthétisable pour de vrais datapaths
Étape 2 · RTL & SoC Architecture
Où mène ce cours.
Le métier autour duquel ce cours est construit, et comment on y entre.
Design Verification Engineer
Prouve qu'une conception de puce fonctionne avant qu'elle parte en fabrication.
Toutes les carrières d'avenirAu quotidien
- Écrire des bancs de test qui cherchent à casser la conception
- Remonter une simulation en échec jusqu'à la ligne de logique qui la cause
- Mesurer la couverture jusqu'à ce que plus rien ne reste non testé
Comment y entrer
En général un diplôme en génie électrique ou en informatique.
Soyez parmi les premiers.
Accès anticipé pour les particuliers, pilotes pour les équipes. Dites-nous qui va apprendre.
enterprise@astratrainer.com